Hierarchical programming language for modal multi-rate real-time stream processing applications

Modal multi-rate stream processing applications with real-time constraints which are executed on multi-core embedded systems often cannot be conveniently specified using current programming languages. An important issue is that sequential programming languages do not allow for convenient programming of multi-rate behavior, whereas parallel programming languages are insufficiently analyzable such that deadlock-freedom and a sufficient throughput cannot be guaranteed.\ud \ud In this paper a programming language is proposed by which a sequential specification of the behavior of an application can be nested in a concurrent specification. Multi-rate behavior can be conveniently expressed using concurrent modules which have well-defined, but restricted interfaces. Complex control behavior can be expressed in the sequential specification of the body of a module. The language is not Turing complete such that a Compositional Temporal Analysis (CTA) model can be derived. It is shown that the CTA model can be used despite the presence of control statements and that the composition of black-box components is possible. Algorithms with a polynomial time complexity can be used to verify whether throughput and latency constraints are met and to determine sufficient buffer capacities.\ud \ud A Phase Alternating Line (PAL) video decoder application is used to demonstrate the applicability of the presented language and analysis approach

Dataflow Analysis for Multiprocessor Systems with Non-Starvation-Free Schedulers

Dataflow analysis techniques are suitable for the temporal analysis of real-time stream processing applications. However, the applicability of these models is currently limited to systems with starvation-free schedulers, such as Time-Division Multiplexing (TDM) schedulers. Removal of this limitation would broaden the application domain of dataflow analysis techniques significantly. In this paper we present a temporal analysis technique for Homogeneous Synchronous Dataflow (HSDF) graphs, that is also applicable for systems with non-starvation-free schedulers. Unlike existing dataflow analysis techniques, the proposed analysis technique makes use of an enabling-jitter characterization and iterative fixed-point computation. The presented approach is applicable for arbitrary (cyclic) graph topologies. Buffer capacity constraints are taken into account during the analysis and sufficient buffer capacities can be determined afterwards. The approach presented in this paper is the first approach that considers non-starvation-free schedulers in combination with arbitrary HSDF graphs. The proposed dataflow analysis technique is implemented in a tool. This tool is used to evaluate the analysis technique using examples that illustrate some important differences with other temporal analysis methods. The case-study discusses how the method presented in this paper can be used to solve a problem with the inaccuracy of the temporal analysis results of a real-time stream processing system. This stream processing system consists of an FM receiver together with a DAB receiver application which both share a Digital Signal Processor (DSP)

A refinement theory for timed-dataflow analysis with support for reordering

Real-time stream processing applications executed on embedded multiprocessor systems often have strict throughput and latency constraints. Violating these constraints is undesired and temporal analysis methods are therefore used to prevent such violations. These analysis methods use abstractions of the analyzed applications to simplify their temporal analysis. \ud \ud Refinement theories have enabled the creation of deterministic abstractions of stream processing applications that are executed on multiprocessor systems. Prominent examples of such abstract models are deterministic timed-dataflow models which can be efficiently analyzed because they only have one behavior. \ud \ud An important aspect of a stream processing application can be that it makes use of reordered data streams between tasks. An example is the bit-reversed ordered stream produced by a FFT task. However, existing abstraction/refinement theories do not support such reordering behavior or do not handle this type of behavior correctly. This is because existing refinement theories assume that the temporal behavior of applications is orthogonal to their functional behavior, whereas this orthogonality does not always hold in the case of reordered data streams.\ud \ud In this paper we introduce a new refinement theory in which the potential interaction between temporal and functional behavior is taken into account. The introduced theory supports reordering of data and can therefore be used to validate existing systems with such reordering. Furthermore, the theory enables showing that deterministic dataflow models that do not apply reordering can be used as valid abstractions of systems in which reordering takes place.\ud \ud The applicability of the refinement theory is demonstrated by creating deterministic timed-dataflow model abstractions of a DVB-T application, and a communication network in which data is reordered. With these dataflow models the guaranteed throughput and buffer capacities of implementation options are compared

Mapping of Modal Applications given Throughput and Latency Constraints

Real-time applications such as software defined radios have different reception modes and their real-time requirements are a result of periodic sources and sinks in the form of ADCs and DACs. Tools are under development that automatically translate a sequential specification of a radio application, that often includes nested while loops to describe the modes, into a parallel task graph and map this task graph onto an embedded multiprocessor system. However the specification of strict periodic sources and sinks together with input and output buffers that can respectively overflow or underrun is currently not possible in a sequential programming language. In this paper we will introduce a nested loop program (NLP) language extension that enables the specification of periodic sources and sinks and their buffers in a sequential program. We show that parallelization of such a sequential program poses challenges because the order in which different tasks access the input and output buffers should be maintained in the parallel program. Furthermore, the buffers at the sources and sinks allow destructive writes and non-destructive reads, which causes non-deterministic functional behavior in case the throughput and latency constraint of the application are not met. The other buffers in the task graph block in case no data or space is available. Therefore, the system internals remain functionally deterministic which significantly simplifies debugging and analysis. Furthermore, to guarantee real-time requirements, we show that it is possible to conservatively model an application with nested while loops as a Cyclo-Static Dataflow (CSDF) model. Using this model we can compute a mapping of the task graph, which includes a task to processor assignment, suitable scheduler settings and buffer capacities. By making use of this CSDF model, we can guarantee that sources and sinks can run periodically under the assumption that the used execution times of the tasks are upper bounds

HAPI: An event-driven simulator for real-time multiprocessor systems

Many embedded multiprocessor systems have hard real-time requirements which should be guaranteed at design time by means of analytical techniques that cover all cases. It is desirable to evaluate the correctness and tightness of the analysis results by means of simulation. However, verification of the analytically obtained results is hampered by the lack of a fast high level simulation approach that supports task scheduling and that does not produce pessimistic simulation traces.\ud \ud In this paper we present HAPI, an event driven simulator for the evaluation of the results of real-time analysis techniques for task graphs executed on multiprocessor systems that support processor sharing. HAPI produces simulation traces that are pessimistic to reality and optimistic to temporal analysis. It can be consequently used to detect optimistic, i.e. incorrect, analysis results.\ud \ud Several task scheduling policies are supported by HAPI such as fixed priority preemptive, time-division multiplex and round-robin. Preemptive task scheduling decisions are simulated which enables to study the cause of delayed task finishes and thereby helps to identify overly pessimistic analysis results.\ud \ud We demonstrate the applicability of the simulator using a number of didactic examples and a WLAN 802.11p application

Compositional temporal analysis method for fixed priority pre-emptive scheduled modal stream processing applications

Modal real-time stream processing applications often contain cyclic dependencies and are typically executed on multiprocessor systems with processor sharing. Most real-time operating system kernels for these systems support Static Priority Pre-emptive (SPP) scheduling, however there is currently no suitable temporal analysis technique available for this type of systems.\ud \ud In this paper, we present a compositional temporal analysis approach for modal and cyclic stream processing applications executed on SPP scheduled multiprocessor systems. In this approach, locks and barriers are added such that the temporal behavior of modes can be characterized independently. As a result, the composition of modes does not change their characterization. This enables the use of an existing Structured Variable-Rate Phased Dataflow (SVPDF) model based dataflow analysis technique to determine the worst-case temporal behavior. The SVPDF model and the parallel implementation including locks and barriers are generated by a multiprocessor compiler. \ud \ud The applicability of the analysis approach is demonstrated using a WLAN 802.11p application. Conditions under which pipelined execution can be achieved are identified. The analysis results are verified with a dataflow simulator that supports sharing of resources

Buffer sizing to reduce interference and increase throughput of real-time stream processing applications

Existing temporal analysis and buffer sizing techniques for real-time stream processing applications ignore that FIFO buffers bound interference between tasks on the same processor. By considering this effect it can be shown that a reduction of buffer capacities can result in a higher throughput. However, the relation between buffer capacities and throughput is non-monotone in general, which makes an exploitation of the effect challenging.\ud \ud In this paper a buffer sizing approach is presented which exploits that FIFO buffers bound interference between tasks on shared processors. The approach combines temporal analysis using a cyclic dataflow model with computation of buffer capacities in an iterative manner and thereby enables higher throughput guarantees at smaller buffer capacities. It is shown that convergence of the proposed analysis flow is guaranteed.\ud \ud The benefits of the presented approach are demonstrated using a WLAN 802.11p transceiver application executed on a multiprocessor system with shared processors. If buffers without blocking writes are used an up to 25% higher guaranteeable throughput and up to 23% smaller buffer capacities can be determined compared to existing approaches. For systems using buffers with blocking writes the guaranteeable throughput is even up to 43% higher and buffer capacities up to 11% smaller

Accuracy improvement of dataflow analysis for cyclic stream processing applications scheduled by static priority preemptive schedulers

Stream processing applications executed on embedded multiprocessor systems regularly contain cyclic data dependencies due to the presence of feedback loops and bounded FIFO buffers. Dataflow modeling is suitable for the temporal analysis of such applications. However, the accuracy can be unsatisfactory as existing temporal analysis techniques ignore that cyclic data dependencies limit interference between tasks executed on shared processors.\ud \ud This paper presents a dataflow analysis approach that increases the analysis accuracy by taking into account that cyclic data dependencies limit interference between tasks. It is shown that the approach is applicable for single-rate stream processing applications that are executed on multiprocessor systems using static priority preemptive schedulers.\ud \ud The improvement of accuracy is demonstrated in a case study employing a WLAN 802.11p transceiver application that is executed on a multiprocessor system with shared processors

Unified dataflow model for the analysis of data and pipeline parallelism, and buffer sizing

Real-time stream processing applications such as software defined radios are usually executed concurrently on multiprocessor systems. Exploiting coarse-grained data parallelism by duplicating tasks is often required, besides pipeline parallelism, to meet the temporal constraints of the applications. However, no unified model and analysis method exists that can be used to determine the required amount of data and pipeline parallelism, and buffer sizes simultaneously.\ud \ud This paper presents an analysis method which can determine the required amount of data parallelism by describing data parallelism in a dataflow model without replicating dataflow actors. This allows to make a trade-off between the amount of data and pipeline parallelism that is required to meet the temporal constraints of the application. It is also shown how large the buffers need to be such that the determined amount of data and pipeline parallelism required for the satisfaction of the throughput constraint, can be realized. Furthermore, it is shown that the use of the applied circular buffers enables the proposed dataflow modeling. \ud \ud The presented analysis method is demonstrated using a WLAN 802.11p transceiver application. This application contains multi-rate behavior and has a cyclic data dependency because of a re-encoding loop. Given the real-time constraints of the application, sufficient buffer sizes and sufficient data parallelism are derived

Compositional Temporal Analysis Model for Incremental Hard Real-Time System Design

The incremental design and analysis of parallel hard real-time stream processing applications is hampered by the lack of an intuitive compositional temporal analysis model that supports arbitrary cyclic dependencies between tasks. This paper introduces a temporal analysis model for hard real-time systems, called the Compositional Temporal Analysis (CTA) model, in which arbitrary cyclic dependencies can be specified. The CTA model also supports hierarchical composition and incremental design of timed components. The internals of a component in the CTA model can be hidden without changing the temporal properties of the component. Furthermore, the composition operation in the CTA model is associative, which enables composing components in an arbitrary order. Besides all these properties, also latency constraints and periodic sources and sinks can be specified and analyzed. We also show in this paper that for the CTA model efficient algorithms exist for buffer sizing, verifying consistency of compositions and to compute the temporal properties of compositions. The CTA model can be used as an abstraction of timed dataflow models. The CTA model uses components with transfer rates per port, in contrast to dataflow models that use actors with firing rules. Unlike dataflow models, the CTA model is not executable. An audio echo cancellation application is used to illustrate the applicability of the CTA model for a stream processing application with throughput and latency constraints, and to illustrate incremental design